View PD750066A_5213836.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

4-bit single-chip microcontrollers the m pd750068 is one of the 75xl series 4-bit single-chip microcontrollers and has a data processing capability comparable to that of an 8-bit microcontroller. the m pd750068 provides more cpu functions compared to the 75x series and realizes high-speed operation at the low voltage of 1.8 v, making it ideal for battery-driven applications. in addition, this device has on-chip a/ d converters, and sophisticated timers capable of operating as a 16-bit timer. the m pd750068(a) has a higher reliability than the m pd750068. a version with on-chip one-time prom, m pd75p0076, is also available for the evaluation during system development or for small-scale production. detailed descriptions of functions are provided in the following document. be sure to read the document before designing. m pd750068 users manual : u10670e document no. u10165ej1v0ds00 (1st edition) date published january 1997 n printed in japan m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) mos integrated circuit features o low-voltage operation: v dd = 1.8 to 5.5 v o on-chip memory ? program memory (rom): 4096 8 bits ( m pd750064, 750064(a)) 6144 8 bits ( m pd750066, 750066(a)) 8192 8 bits ( m pd750068, 750068(a)) ? data memory (ram): 512 4 bits o variable instruction execution time for high-speed operation and power-saved operation ? 0.95, 1.91, 3.81, 15.3 m s (@ 4.19 mhz) ? 0.67, 1.33, 2.67, 10.7 m s (@ 6.0 mhz) ? 122 m s (@ 32.768 khz) o internal low-voltage a/d converters (av ref = 1.8 to 5.5 v) 8-bit resolution 8 channels o small packages (shrink sop, shrink dip) o uses instructions of 75x series for easy replacement applications o m pd750064, 750066, 750068 cordless phones, audio-visual equipment, home appliances, office machines, fitness machines, meters, gas ranges, etc. o m pd750064(a), 750066(a), 750068(a) electrical equipment for automobiles the m pd750064, 750066, 750068 and m pd750064(a), 750066(a), 750068(a) differ only in quality grade. in this manual, the m pd750068 is described as typical product unless otherwise specified. users of other than the m pd750068 should read the m pd750068 as referring to the pertinent product. when the description differs among the m pd750064, 750066, and 750068, they also refer to the pertinent (a) products. m pd750064 ? m pd750064(a), m pd750066 ? m pd750066(a), m pd750068 ? m pd750068(a) the information in this document is subject to change without notice. the mark shows major revised points. 1995 data sheet
2 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) ordering information part number package quality grade m pd750064cu- 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) standard m pd750064gt- 42-pin plastic shrink sop (375 mil, 0.8 mm pitch) standard m pd750066cu- 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) standard m pd750066gt- 42-pin plastic shrink sop (375 mil, 0.8 mm pitch) standard m pd750068cu- 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) standard m pd750068gt- 42-pin plastic shrink sop (375 mil, 0.8 mm pitch) standard m pd750064cu(a)- 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) special m pd750064gt(a)- 42-pin plastic shrink sop (375 mil, 0.8 mm pitch) special m pd750066cu(a)- 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) special m pd750066gt(a)- 42-pin plastic shrink sop (375 mil, 0.8 mm pitch) special m pd750068cu(a)- 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) special m pd750068gt(a)- 42-pin plastic shrink sop (375 mil, 0.8 mm pitch) special remark is rom code suffix. please refer to quality grade on nec semiconductor devices (document number c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. differences between m pd75006 and m pd75006 (a) part number m pd750064 m pd750064(a) m pd750066 m pd750066(a) item m pd750068 m pd750068(a) quality grade standard special
3 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) functional outline parameter function instruction execution time ? 0.95 m s, 1.91 m s, 3.81 m s, 15.3 m s (@ 4.19 mhz with main system clock) ? 0.67 m s, 1.33 m s, 2.67 m s, 10.7 m s (@ 6.0 mhz with main system clock) ? 122 m s (@ 32.768 khz with subsystem clock) on-chip memory rom 4096 8 bits ( m pd750064) 6144 8 bits ( m pd750066) 8192 8 bits ( m pd750068) ram 512 4 bits general-purpose register ? 4-bit operation: 8 4 banks ? 8-bit operation: 4 4 banks input/ cmos input 12 on-chip pull-up resistors can be specified by software: 7 output also used for analog input pins: 4 port cmos input/output 12 on-chip pull-up resistors can be specified by software: 12 also used for analog input pins: 4 n-ch open-drain 8 13 v withstand voltage input/output pins on-chip pull-up resistors can be specified by mask option total 32 timer 4 channels ? 8-bit timer/event counter: 2 channels (can be used as the 16-bit timer/event counter) ? basic interval timer/watchdog timer: 1 channel ? watch timer: 1 channel serial interface ? 3-wire serial i/o mode msb or lsb can be selected for transferring first bit ? 2-wire serial i/o mode a/d converter 8-bit resolution 8 channels (1.8 v - av ref - v dd ) bit sequential buffer 16 bits clock output (pcl) ? f , 1.05 mhz, 262 khz, 65.5 khz (@ 4.19 mhz with main system clock) ? f , 1.5 mhz, 375 khz, 93.8 khz (@ 6.0 mhz with main system clock) buzzer output (buz) ? 2 khz, 4 khz, 32 khz (@ 4.19 mhz with main system clock or @ 32.768 khz with subsystem clock) ? 2.93 khz, 5.86 khz, 46.9 khz (@ 6.0 mhz with main system clock) vectored interrupt external: 3, internal: 4 test input external: 1, internal: 1 system clock oscillator ? ceramic or crystal oscillator for main system clock oscillation ? crystal oscillator for subsystem clock oscillation standby function stop/halt mode operating ambient temperature t a = C40 to +85 c power supply voltage v dd = 1.8 to 5.5 v package ? 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) ? 42-pin plastic shrink sop (375 mil, 0.8 mm pitch)
4 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) contents 1. pin configuration (top view) ..................................................................................................... 6 2. block diagram .............................................................................................................................. 7 3. pin function ................................................................................................................................... 8 3.1 port pins .................................................................................................................................... 8 3.2 non-port pins ........................................................................................................................... 10 3.3 pin input/output circuits ........................................................................................................ 12 3.4 recommended connections for unused pins ...................................................................... 15 4. switching function between mk i mode and mk ii mode ............................................... 16 4.1 differences between mk i mode and mk ii mode ................................................................... 16 4.2 setting method of stack bank select register (sbs) .......................................................... 17 5. memory configuration............................................................................................................ 18 6. peripheral hardware function .......................................................................................... 23 6.1 port ........................................................................................................................................... 23 6.2 clock generator ...................................................................................................................... 23 6.3 subsystem clock oscillator control function ..................................................................... 25 6.4 clock output circuit ............................................................................................................... 26 6.5 basic interval timer/watchdog timer ................................................................................... 27 6.6 watch timer ............................................................................................................................. 28 6.7 timer/event counter ............................................................................................................... 29 6.8 serial interface ......................................................................................................................... 32 6.9 a/d converter .......................................................................................................................... 33 6.10 bit sequential buffer ............................................................................................................... 34 7. interrupt function and test function ............................................................................. 35 8. standby function ...................................................................................................................... 37 9. reset function ........................................................................................................................... 38 10. mask option .................................................................................................................................. 41 11. instruction set .......................................................................................................................... 42 12. electrical specifications ..................................................................................................... 55 13. characteristic curves (for referecnce only) ............................................................ 68 14. package drawings .................................................................................................................... 70 15. recommended soldering conditions ................................................................................ 72
5 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) appendix a. m m m m m pd75068, 750068 and 75p0076 functional list ................................................. 73 appendix b. development tools ................................................................................................ 75 appendix c. related documents ............................................................................................... 79
6 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 1. pin configuration (top view) ? 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) m pd750064cu- , m pd750064cu(a)- m pd750066cu- , m pd750066cu(a)- m pd750068cu- , m pd750068cu(a)- ? 42-pin plastic shrink sop (375 mil, 0.8 mm pitch) m pd750064gt- , m pd750064gt(a)- m pd750066gt- , m pd750066gt(a)- m pd750068gt- , m pd750068gt(a)- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 xt1 xt2 reset x1 x2 p33 p32 p31 p30 av ss p63/kr3/an7 p62/kr2/an6 p61/kr1/an5 p60/kr0/an4 p113/an3 p112/an2 p111/an1 p110/an0 av ref ic v dd v ss p40 p41 p42 p43 p50 p51 p52 p53 p00/int4 p01/sck p02/so/sb0 p03/si/sb1 p10/int0 p11/int1 p12/ti1/int2 p13/ti0 p20/pto0 p21/pto1 p22/pcl p23/buz ic: internally connected (connect pin directly to v dd ). pin identification an0-an7 : analog input 0-7 av ref : analog reference av ss : analog ground buz : buzzer clock ic : internally connected int0, int1, int4 : external vectored interrupt 0, 1, 4 int2 : external test input 2 kr0-kr3 : key return 0-3 p00-p03 : port 0 p10-p13 : port 1 p20-p23 : port 2 p30-p33 : port 3 p40-p43 : port 4 p50-p53 : port 5 p60-p63 : port 6 p110-p113 : port 11 pcl : programmable clock pto0, pto1 : programmable timer output 0, 1 reset : reset input sb0, sb1 : serial data bus 0, 1 sck : serial clock si : serial input so : serial output ti0, ti1 : timer input 0, 1 v dd : positive power supply v ss : ground x1, x2 : main system clock oscillation 1, 2 xt1, xt2 : subsystem clock oscillation 1, 2
7 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 2. block diagram basic interval timer/watchdog timer watch timer 8-bit timer/ event counter#0 8-bit timer/ event counter#1 cascaded 16-bit timer/ event counter clocked serial interface interrupt control a/d converter intbt intw intt0 intw intt1 tout0 intcsi buz/p23 ti0/p13 pto0/p20 ti1/p12/int2 pto1/p21 si/sb1/p03 so/sb0/p02 sck/p01 int0/p10 int1/p11 int4/p00 int2/p12/ti1 kr0/p60 - kr3/p63 an0/p110 - an3/p113 an4/p60 - an7/p63 av ref av ss cy sp (8) sbs bank program counter program memory note (rom) decode and control general reg. data memory (ram) 512 4bits port0 port1 port2 port3 port4 port5 port6 port11 bit seq. buffer (16) p00 - p03 4 4 4 4 4 4 p10 - p13 p20 - p23 p30 - p33 p40 - p43 p50 - p53 p60 - p63 p110 - p113 fx/2 n cpu clock f clock output control clock divider sub main system clock generator stand by control pcl/p22 xt1 xt2 x1 x2 ic v dd v ss reset alu 4 4 4 4 4 note capacity of the rom depends on the product.
8 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 3. pin function 3.1 port pins (1/2) pin name input/output dual description 8-bit after reset i/o circuit function pin i/o type note 1 p00 input int4 no input p01 input/output sck -a p02 input/output so/sb0 -b p03 input/output si/sb1 -c p10 input int0 no input -c p11 int1 p12 ti1/int2 p13 ti0 p20 input/output pto0 no input e-b p21 pto1 p22 pcl p23 buz p30-p33 input/output C no input e-b p40-p43 note 2 input/output C yes m-d p50-p53 note 2 input/output C m-d notes 1. circuit types enclosed in brackets indicate the schmitt trigger input. 2. if on-chip pull-up resistors are not specified by mask option (when used as n-ch open-drain input port), low level input leakage current increases when input or bit manipulation instruction is executed. high level (when pull-up resistors are provided) or high- impedance 4-bit input port (port0). for p01 to p03, connection of on-chip pull- up resistors can be specified by software in 3-bit units. 4-bit input port (port1). connection of on-chip pull-up resistors can be specified by software in 4-bit units. p10/int0 can select noise elimination circuit. 4-bit input/output port (port2). connection of on-chip pull-up resistors can be specified by software in 4-bit units. programmable 4-bit input/output port (port3). this port can be specified for input/output bit-wise. connection of on-chip pull-up resistor can be specified by software in 4-bit units. n-ch open-drain 4-bit input/output port (port4). a pull-up resistor can be contained bit- wise (mask option). withstand voltage is 13 v in open-drain mode. n-ch open-drain 4-bit input/output port (port5). a pull-up resistor can be contained bit-wise (mask option). withstand voltage is 13 v in open-drain mode. high level (when pull-up resistors are provided) or high- impedance
9 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 3.1 port pins (2/2) pin name input/output dual description 8-bit after reset i/o circuit function pin i/o type note p60 input/output kr0/an4 no input -d p61 kr1/an5 p62 kr2/an6 p63 kr3/an7 p110 input an0 no input y-a p111 an1 p112 an2 p113 an3 note circuit types enclosed in brackets indicate the schmitt trigger input. programmable 4-bit input/output port (port6). this port can be specified for input/output bit- wise. connection of on-chip pull-up resistors can be specified by software in 4-bit units. 4-bit input port (port11).
10 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 3.2 non-port pins (1/2) pin name input/output dual description after reset i/o circuit function pin type note ti0 input p13 inputs external event pulses to the timer/event input -c ti1 p12/int2 counter. pto0 output p20 timer/event counter output input e-b pto1 p21 pcl p22 clock output buz p23 optional frequency output (for buzzer output or system clock trimming) sck input/output p01 serial clock input/output input -a so output p02 serial data output -b sb0 input/output serial data bus input/output si input p03 serial data input -c sb1 input/output serial data bus input/output int4 input p00 edge detection vectored interrupt input (both input rising edge and falling edge detection) int0 input p10 input -c int1 p11 asynchronous int2 input p12/ti1 rising edge detection asynchronous input -c testable input kr0-kr3 input p60/an4- falling edge detection testable input input -d p63/an7 an0-an3 input p110-p113 analog signal input input y-a an4-an7 p60/kr0- -d p63/kr3 av ref C C a/d converter reference voltage C z-n av ss C C a/d converter reference gnd potential C z-n note circuit types enclosed in brackets indicate the schmitt trigger input. edge detection vectored noise elimination interrupt input (detection circuit/asynchronous edge can be selected). selection int0/p10 can select noise elimination circuit.
11 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 3.2 non-port pins (2/2) pin name input/output dual description after reset i/o circuit function pin type note x1 input C C C x2 C xt1 input C C C xt2 C reset input C system reset input (low-level active) C ic C C internally connected. connect directly to v dd .C C v dd C C positive power supply C C v ss C C ground potential C C note circuit types enclosed in brackets indicate the schmitt trigger input. crystal/ceramic connection pin for the main system clock oscillation. when inputting the external clock, input the external clock to pin x1, and the inverted phase of the external clock to pin x2. crystal connection pin for the subsystem clock oscillation. when the external clock is used, input the external clock to pin xt1, and the inverted phase of the external clock to pin xt2. pin xt1 can be used as a 1-bit input (test) pin.
12 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 3.3 pin input/output circuits the m pd750068 pin input/output circuits are shown schematically. (1/3) type a type b type d type e-b type b-c type f-a v dd in p-ch n-ch data output disable n-ch p-ch in out v dd p-ch output disable data p.u.r. enable type d type a in/out v dd p.u.r. enable p.u.r. p-ch in v dd p.u.r. p.u.r. enable p-ch in/out type d type b output disable data p.u.r. : pull-up resistor p.u.r. : pull-up resistor p.u.r. : pull-up resistor schmitt trigger input with hysteresis characteristics cmos standard input buffer push-pull output that can be placed in output high-impedance (both p-ch and n-ch off). p.u.r. v dd
13 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) (2/3) output disable (p) output disable data output disable (n) p.u.r. enable p-ch p.u.r. in/out p-ch n-ch v dd v dd p.u.r. : pull-up resistor type f-b type y in p-ch n-ch v dd v dd av ss av ss input enable reference voltage (from the voltage tap of the series resistor string) type y-a input butfer type a type y in type m-c output disable data p.u.r. enable p-ch p.u.r. in/out n-ch v dd p.u.r. : pull-up resistor type m-d in instruction sampling c + p.u.r. note v dd n-ch in/out p.u.r. (mask option) data output disable note this pull-up resistor operates only when an input instruction is executed without a pull-up resistor connected using the mask option (current flows from v dd to the pin when the pin is low). input instruction v dd p-ch (+13 v withstand voltage) (+13 v withstand voltage) voltage limitation circuit
14 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) (3/3) type z-n p.u.r. enable p.u.r. v dd p-ch in/out p.u.r.: pull-up resistor type y-d data output disable type y type d type b aden reference voltage av ref n-ch av ss
15 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 3.4 recommended connections for unused pins table 3-1. list of recommended connections for unused pins pin recommended connection p00/int4 connect to v ss or v dd p01/sck connect to v ss or v dd via a resistor individually p02/so/sb0 p03/si/sb1 connect to v ss p10/int0, p11/int1 connect to v ss or v dd p12/ti1/int2 p13/ti0 p20/pto0 input state: connect to v ss or v dd via a resistor p21/pto1 individually p22/pcl output state: open p23/buz p30-p33 p40-p43 connect to v ss (do not connect a pull-up resistor p50-p53 of mask option) p60/kr0/an4-p63/kr3/an7 input state: connect to v ss or v dd via a resistor individually output state: open p110/an0-p113/an3 connect to v ss or v dd directly xt1 note connect to v ss or v dd xt2 note open ic connect to v dd directly av ref connect to v ss av ss note when the subsystem clock is not used, set sos.0 to 1 (so as not to use the internal feedback resistor).
16 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 4. switching function between mk i mode and mk ii mode 4.1 differences between mk i mode and mk ii mode the cpu of the m pd750068 has the following two modes: mk i and mk ii, either of which can be selected. the mode can be switched by the bit 3 of the stack bank select register (sbs). ? mk i mode: upward compatible with m pd75068. can be used in the 75xl cpu with a rom capacity of up to 16 kbytes. ? mk ii mode: incompatible with m pd75068. can be used in all the 75xl cpus including those products whose rom capacity is more than 16 kbytes. table 4-1. differences between mk i mode and mk ii mode mk i mode mk ii mode number of stack bytes 2 bytes 3 bytes for subroutine instructions bra !addr1 instruction not available available calla !addr1 instruction call !addr instruction 3 machine cycles 4 machine cycles callf !faddr instruction 2 machine cycles 3 machine cycles caution the mk ii mode supports a program area exceeding 16 kbytes for the 75x and 75xl series. therefore, this mode is effective for enhancing software compatibility with products exceeding 16 kbytes. when the mk ii mode is selected, the number of stack bytes used during execution of subroutine call instructions increases by one byte per stack compared to the mk i mode. when the call !addr and callf !faddr instructions are used, the machine cycle becomes longer by one machine cycle. therefore, use the mk i mode if the ram efficiency and processing performance are more important than software compatibility.
17 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 4.2 setting method of stack bank select register (sbs) switching between the mk i mode and mk ii mode can be done by the stack bank select register (sbs). figure 4-1 shows the format. the sbs is set by a 4-bit memory manipulation instruction. when using the mk i mode, the sbs must be initialized to 100 b note at the beginning of a program. when using the mk ii mode, it must be initialized to 000 b note . note set the desired value in the position. figure 4-1. stack bank select register format sbs3 sbs2 sbs1 sbs0 3210 symbol sbs address f84h 00 01 0 1 0 memory bank 0 memory bank 1 other than above setting prohibited 0 must be set in the bit 2 position. stack area specification mk ii mode mk i mode mode switching specification caution since sbs. 3 is set to 1 after a reset signal is generated, the cpu operates in the mk i mode. when executing an instruction in the mk ii mode, set sbs. 3 to 0 to select the mk ii mode.
18 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 5. memory configuration program memory (rom) .... 4096 8 bits ( m pd750064) .... 6144 8 bits ( m pd750066) .... 8192 8 bits ( m pd750068) ? addresses 0000h and 0001h vector table wherein the program start address and the values set for the rbe and mbe at the time a reset signal is generated are written. reset start is possible from any address. ? addresses 0002h to 000dh vector table wherein the program start address and the values set for the rbe and mbe by each vectored interrupt are written. interrupt processing can start from any address. ? addresses 0020h to 007fh table area referenced by the geti instruction note . note the geti instruction realizes a 1-byte instruction on behalf of any 2-byte instruction, 3-byte instruction, or two 1-byte instructions. it is used to decrease the number of program steps. data memory (ram) ? data area .... 512 words 4 bits (000h to 1ffh) ? peripheral hardware area .... 128 words 4 bits (f80h to fffh)
19 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) figure 5-1. program memory map ( m m m m m pd750064) 000h address 7654 mbe rbe 0 0 internal reset start address (high-order 4 bits) 0 002h mbe rbe 0 0 intbt/int4 (high-order 4 bits) start address 004h mbe rbe 0 0 int0 (high-order 4 bits) start address 006h mbe rbe 0 0 int1 (high-order 4 bits) start address 008h mbe rbe 0 0 intcsi (high-order 4 bits) start address 00ah mbe rbe 0 0 intt0 (high-order 4 bits) start address 00ch mbe rbe 0 0 intt1 (high-order 4 bits) start address 020h 07fh 080h 7ffh 800h fffh geti instruction reference table (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) callf ! faddr instruction entry address branch address of br bcxa, br bcde, br !addr, bra !addr1 note or calla !addr1 note instruction call !addr instruction subroutine entry address br $addr instruction relative branch address brcb !caddr instruction branch address ?5 to ?, +2 to +16 branch destination address and subroutine entry address when geti instruction is executed internal reset start address intbt/int4 start address int0 start address int1 start address intcsi start address intt0 start address intt1 start address note can be used only in the mk ii mode. remark in addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of pc by executing the br pcde or br pcxa instruction.
20 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) figure 5-2. program memory map ( m m m m m pd750066) 0000h address 0002h mbe rbe 0 intbt/int4 (high-order 5 bits) start address 0004h mbe rbe 0 int0 (high-order 5 bits) start address 0006h mbe rbe 0 int1 (high-order 5 bits) start address 0008h mbe rbe 0 intcsi (high-order 5 bits) start address 000ah mbe rbe 0 intt0 (high-order 5 bits) start address 0020h 007fh 0080h 07ffh 0800h mbe rbe 0 internal reset start address (high-order 5 bits) 0fffh 1000h 17ffh geti instruction reference table 000ch mbe rbe 0 intt1 (high-order 5 bits) start address (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) callf ! faddr instruction entry address brcb ! caddr instruction branch address branch address of br bcxa, br bcde, br ! addr, bra ! addr1 note or calla ! addr1 note instruction call ! addr instruction subroutine entry address br $ addr instruction relative branch address ?5 to ?, +2 to +16 branch destination address and subroutine entry address when geti instruction is executed brcb ! caddr instruction branch address 765 0 internal reset start address intbt/int4 int0 int1 intcsi intt0 intt1 start address start address start address start address start address start address note can be used only in the mk ii mode. remark in addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of pc by executing the br pcde or br pcxa instruction.
21 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) figure 5-3. program memory map ( m m m m m pd750068) 0000h address 0002h mbe rbe 0 intbt/int4 (high-order 5 bits) start address 0004h mbe rbe 0 int0 (high-order 5 bits) start address 0006h mbe rbe 0 int1 (high-order 5 bits) start address 0008h mbe rbe 0 intcsi (high-order 5 bits) start address 000ah mbe rbe 0 intt0 (high-order 5 bits) start address 0020h 007fh 0080h 07ffh 0800h mbe rbe 0 internal reset start address (high-order 5 bits) 0fffh 1000h 1fffh geti instruction reference table 000ch mbe rbe 0 intt1 (high-order 5 bits) start address (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) callf ! faddr instruction entry address brcb ! caddr instruction branch address branch address of br bcxa, br bcde, br ! addr, bra ! addr1 note or calla ! addr1 note instruction call ! addr instruction subroutine entry address br $ addr instruction relative branch address ?5 to ?, +2 to +16 branch destination address and subroutine entry address when geti instruction is executed brcb ! caddr instruction branch address 765 0 internal reset start address intbt/int4 int0 int1 intcsi intt0 intt1 start address start address start address start address start address start address note can be used only in the mk ii mode. remark in addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of pc by executing the br pcde or br pcxa instruction.
22 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) figure 5-4. data memory map data area static ram (512 4) stack area note general-purpose register area 000h 01fh 020h 0ffh 100h f80h fffh peripheral hardware area data memory memory bank 0 (32 4) (224 4) 256 4 256 4 not incorporated 128 4 15 1 1ffh note memory bank 0 or 1 can be selected as the stack area.
23 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 6. peripheral hardware function 6.1 port there are three types of i/o ports as follows. ? cmos input (port0, 1, 11) : 12 ? cmos input/output (port2, 3, 6) : 12 ? n-ch open drain input/output (port4, 5) : 8 total 32 table 6-1. types and features of digital ports port name function operation and features remarks port0 4-bit input when the serial interface function is used, the dual function pins also used for the int4, sck, function as output ports depending on the operation mode. so/sb0, si/sb1 pins. port1 4-bit input only port. also used for the int0-int2/ ti1, ti0 pins. port2 4-bit input/output can be set to input mode or output mode in 4-bit units. also used for the pto0, pto1, pcl, buz pins. port3 can be set to input mode or output mode bit-wise. C port4 4-bit input/output can be set to input mode or output ports 4 and 5 are paired port5 (n-ch open drain, mode in 4-bit units. on-chip pull-up and data can be input/ 13 v withstand resistor can be specified bit-wise output in 8-bit units. voltage) by mask option. port6 4-bit input/output can be set to input mode or output mode bit-wise. also used for the kr0-kr3, an4-an7 pins. port11 4-bit input 4-bit input only port. also used for the an0-an3 pins. 6.2 clock generator the clock generator generates clocks which are supplied to the peripheral hardware in the cpu. figure 6-1 shows the configuration of the clock generator. operation of the clock generator is determined by the processor clock control register (pcc) and system clock control register (scc). two types of system clocks are available; main system clock and subsystem clock. the instruction execution time can also be changed. ? 0.95 m s, 1.91 m s, 3.81 m s, 15.3 m s (@ 4.19 mhz with main system clock) ? 0.67 m s, 1.33 m s, 2.67 m s, 10.7 m s (@ 6.0 mhz with main system clock) ? 122 m s (@ 32.768 khz with subsystem clock)
24 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) figure 6-1. clock generator block diagram xt1 x1 xt2 x2 f xt f x subsystem clock oscillator main system clock oscillator 4 halt note stop note wm.3 scc scc3 scc0 pcc0 pcc1 pcc2 pcc3 pcc2, pcc3 clear stop f/f q s r oscillation stop halt f/f s r wait release signal from bt reset signal standby release signal from interrupt control circuit ?cpu ?int0 noise eliminator ?clock output circuit f 1/4 divider 1/1 to 1/4096 divider 1/2 1/4 1/16 ?basic interval timer (bt) ?timer/event counter ?serial interface ?watch timer ?int0 noise eliminator ?clock output circuit pcc q selector selector internal bus watch timer note instruction execution remarks 1. f x = main system clock frequency 2. f xt = subsystem clock frequency 3. f = cpu clock 4. pcc: processor clock control register 5. scc: system clock control register 6. one clock cycle (t cy ) of the cpu clock is equal to one machine cycle of the instruction.
25 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 6.3 subsystem clock oscillator control function the subsystem clock oscillator of the m pd750068 has the following two control functions to decrease the supply current. ? selects by software whether an internal feedback resistor is to be used or not note . ? reduces current consumption by decreasing the drive current of the on-chip inverter when the supply voltage is high (v dd ? 2.7 v). note when the subsystem clock is not used, set sos.0 to 1 (so as not to use the internal feedback resistor) by software, connect xt1 to v ss or v dd , and open xt2. this makes it possible to reduce the current consumption in the subsystem clock oscillator. the above functions can be used by switching the bits 0 and 1 of the sub-oscillator control register (sos). (refer to figure 6-2.) figure 6-2. subsystem clock oscillator feedback resistor sos.0 sos.1 xt1 xt2 inverter
26 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 6.4 clock output circuit the clock output circuit is provided to output the clock pulses from the p22/pcl pin to the remote control wave outputs and peripheral lsis. ? clock output (pcl) : f , 1.05 mhz, 262 khz, 65.5 khz (at 4.19 mhz) : f , 1.5 mhz, 375 khz, 93.8 khz (at 6.0 mhz) figure 6-3. clock output circuit block diagram from clock generator f f x /2 2 f x /2 4 f x /2 6 selector clom3 0 clom1 clom0 4 clom p22 output latch port 2 i/o mode specification bit port2.2 bit 2 of pmgb internal bus output buffer pcl/p22 remark special care has been taken in designing the chip so that small-width pulses may not be output when switching clock output enable/disable.
27 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 6.5 basic interval timer/watchdog timer the basic interval timer/watchdog timer has the following functions. (a) interval timer operation to generate a reference time interrupt (b) watchdog timer operation to detect a runaway of program and reset the cpu (c) selects and counts the wait time when the standby mode is released (d) reads the contents of counting figure 6-4. basic interval timer/watchdog timer block diagram from clock generator f x /2 5 f x /2 7 f x /2 9 f x /2 12 mpx btm3 btm2 btm1 btm0 btm 4 set1 note internal bus 81 basic interval timer (8-bit frequency divider) clear bt wait release signal when standby is released set clear 3 wdtm set1 note internal reset signal vectored interrupt request signal bt interrupt request flag irqbt note instruction execution
28 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 6.6 watch timer the m pd750068 has one channel of watch timer. the watch timer has the following functions. (a) sets the test flag (irqw) with 0.5 sec interval. the standby mode can be released by the irqw. (b) 0.5 sec interval can be created by both the main system clock (4.194304 mhz) and subsystem clock (32.768 khz). (c) convenient for program debugging and checking as interval becomes 128 times longer (3.91 ms) with the fast feed mode. (d) outputs the frequencies (2.048, 4.096, 32.768 khz) to the p23/buz pin, usable for buzzer and trimming of system clock frequencies. (e) clears the frequency divider to make the clock start with zero seconds. (f) uses the clock of 0.5 sec as the clock source of the timer/event counter to continue the standby mode until the longest time 9 hours (by using timer 0, 1) to be in the lowest consumption mode. figure 6-5. watch timer block diagram from clock generator selector f x 128 (32.768 khz) f xt (32.768 khz) f w (32.768 khz) divider 4 khz 2 khz f w 2 3 f w 2 4 clear selector f w 2 7 (256 hz : 3.91 ms) f w 2 14 selector 2 hz 0.5 sec irqw set signal intw output buffer pmgb bit 2 port2.3 wm wm7 0 wm5 wm4 wm3 wm2 wm1 wm0 p23 output latch port 2 input/ output mode 8 internal bus bit test instruction p23/buz remark the values enclosed in parentheses are applied when f x = 4.194304 mhz and f xt = 32.768 khz.
29 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 6.7 timer/event counter the m pd750068 has two channels of timer/event counters. its configuration is shown in figures 6-6 and 6-7. the timer/event counter has the following functions. (a) programmable interval timer operation (b) square wave output of any frequency to the pton pin (n = 0, 1) (c) event counter operation (d) divides the frequency of signal input via the tin pin to 1-nth of the original signal and outputs the divided frequency to the pton pin (frequency divider operation). (e) supplies the shift clock to the serial interface circuit. (f) reads the count value. the timer/event counter operates in the following two modes as set by the mode register. table 6-2. operation modes of timer/event counter channel channel 0 channel 1 mode 8-bit timer/event counter mode yes yes 16-bit timer/event counter mode yes
30 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) figure 6-6. timer/event counter block diagram (channel 0) timer/event counter tm06 modulo register (8) tm05 tm04 tm03 tm02 tm01 tm00 8 tm0 decoder internal bus 8 port1. 3 input buffer ti0/p13 watch timer (intw) output from clock generator f x /2 2 f x /2 4 f x /2 6 f x /2 8 f x /2 10 mpx tmod0 8 comparator (8) count register (8) cp clear reset t0 16-bit timer/event counter mode timer operation start timer/event counter (channel 1) tm12 signal (when 16-bit timer/event counter mode) timer/event counter (channel 1) match signal (when 16-bit timer/event counter mode) timer/event counter (channel 1) clear signal (when 16-bit timer/event counter mode) overflow tout0 toe0 tout f/f port2.0 pmgb bit 2 to p20 to serial interface p20/pto0 output buffer (channel 1) clock input intt0 (irqt0 set signal) irqt0 clear signal reset 8 match enable flag output latch port 2 input/ output mode
31 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) figure 6-7. timer/event counter block diagram (channel 1) port1.2 input buffer ti1/p12/int2 timer/event counter output (channel 0) from clock generator mpx tm16 tm15 tm14 tm13 tm12 tm11 tm10 tm1 decoder 16 bit timer/event counter mode cp timer operation start clear 8 8 8 8 modulo register (8) comparator (8) count register (8) timer/event counter (channel 0) match signal/operation start (when 16-bit timer/event counter mode) timer/event counter (channel 0) comparator (when 16-bit timer/event counter mode) t1 tmod1 match tout f/f reset t1 enable flag p21 output latch port 2 input/output mode intt1 irqt1 set signal irqt1 clear signal reset toe1 port2.1 pmgb bit 2 p21/pto1 output buffer internal bus timer/event counter (channel 0) tm02 signal (when 16-bit timer/event counter mode) selector f x /2 2 f x /2 6 f x /2 8 f x /2 10 f x /2 12
32 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 6.8 serial interface the serial interface has the following three modes. ? operation stop mode ? 3-wire serial i/o mode ? 2-wire serial i/o mode the 3-wire serial i/o mode enables connections to be made with the 75x series, 78k series, and many other types of i/o devices. the 2-wire serial i/o mode enables communication with two or more devices. figure 6-8. serial interface block diagram internal bus 8/4 bit test p03/si/sb1 p02/so/sb0 p01/sck 88 sbic relt cmdt set clr dq (8) intcsi ? t ? t irqcsi set signal f x /2 3 f x /2 4 f x /2 6 tout0 ? t ? t p01 output latch selector selector serial clock counter serial clock control circuit serial clock selector so latch shift register (sio) external sck from timer/event counter 0 bit manipu- lation intcsi control circuit csim
33 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 6.9 a/d converter the m pd750068 incorporates the 8-bit resolution a/d converter which has eight channels analog input pins (an0-an7). this a/d converter is a successive approximation type. figure 6-9. a/d converter block diagram + internal bus 8 aden adm6 adm5 adm4 soc eoc 0 0 controller sample hold circuit comparator sa register (8) 8 8 tap decoder multiplexer an0/p110 an1/p111 an2/p112 an3/p113 an4/p60/kr0 an5/p61/kr1 an6/p62/kr2 an7/p63/kr3 av ref av ss r/2 r r r r/2 aden
34 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 6.10 bit sequential buffer ....... 16 bits the bit sequential buffer (bsb) is a special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it is useful when processing a long data bit-wise. figure 6-10. bit sequential buffer format address bit symbol l register l = fh l = ch l = bh l = 8h l = 7h l = 4h l = 3h l = 0h decs l incs l bsb3 bsb2 bsb1 bsb0 3210321032103210 fc3h fc2h fc1h fc0h remarks 1. in the pmem.@l addressing, the specified bit moves corresponding to the l register. 2. in the pmem.@l addressing, the bsb can be manipulated regardless of mbe/mbs specification.
35 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 7. interrupt function and test function the m pd750068 has seven interrupt sources and two test sources. one test source, int2, has two types of edge detection testable inputs. the interrupt control circuit of the m pd750068 has the following functions. (1) interrupt function ? vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the interrupt enable flag (ie ) and interrupt master enable flag (ime). ? can set any interrupt start address. ? multiple interrupts wherein the order of priority can be specified by the interrupt priority select register (ips). ? test function of interrupt request flag (irq ). an interrupt generated can be checked by software. ? release the standby mode. a release interrupt can be selected by the interrupt enable flag. (2) test function ? test request flag (irq ) generation can be checked by software. ? release the standby mode. the test source to be released can be selected by the test enable flag.
36 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) figure 7-1. interrupt control circuit block diagram ist0 ist1 internal bus interrupt enable flag (ie ) irqbt irq4 irq0 irq1 irqcsi irqt0 irqt1 irqw irq2 intcsi intt0 intt1 intw both edge detector edge detector edge detector selector int4/p00 int0/p10 int1/p11 int2/p12 kr0/p60 kr3/p63 rising edge detector falling edge detector selector im2 standby release signal priority control circuit vector table address generator vrqn im2 im0 214 intbt note ime ips decoder im1 note noise elimination circuit (standby release is disabled when noise elimination circuit is selected.)
37 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 8. standby function in order to save power dissipation while a program is in a standby mode, two types of standby modes (stop mode and halt mode) are provided for the m pd750068. table 8-1. operation status in standby mode mode stop mode halt mode item set instruction stop instruction halt instruction system clock when set settable only when the main system settable both by the main system clock clock is used. and subsystem clock. operation clock generator the main system clock stops oscillation. only the cpu clock f halts (oscillation status continues). basic interval timer/ operation stops. operable only when the main system watchdog timer clock is oscillated (the irqbt is set in the reference time interval). serial interface operable only when an external sck operable only when an external sck input is selected as the serial clock. input is selected as the serial clock or when the main system clock is oscillated. timer/event counter operable only when a signal input to operable only when a signal input to the ti0 and ti1 pins or a watch timer the ti0 and ti1 pins or a watch timer which selected f xt is specified as the which selected f xt is specified as the count clock. count clock or when the main system clock is oscillated. watch timer operable when f xt is selected as the operable. count clock. a/d converter operation stops. operable only when the main system clock is oscillated. external interrupt the int1, 2, and 4 are operable. only the int0 is not operated note . cpu operation stops. release signal interrupt request signal sent from the operable hardware enabled by the interrupt enable flag or reset signal input. note can operate only when the noise elimination circuit is not used (im02 = 1) by bit 2 of the edge detection mode register (im0).
38 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 9. reset function there are two reset inputs: external reset signal (reset) and reset signal sent from the basic interval timer/ watchdog timer. when either one of the reset signals are input, an internal reset signal is generated. figure 9- 1 shows the configuration of the above two inputs. figure 9-1. configuration of reset function reset internal reset signal reset signal sent from the basic interval timer/watchdog timer wdtm internal bus when the reset signal is generated, each hardware is initialized as listed in table 9-1. figure 9-2 shows the timing chart of the reset operation. figure 9-2. reset operation by reset signal generation operation mode or standby mode wait note reset signal generated operation mode halt mode internal reset operation note the following two times can be selected by the mask option. 2 17 /f x (21.8 ms: during 6.0-mhz operation, 31.3 ms: during 4.19-mhz operation) 2 15 /f x (5.46 ms: during 6.0-mhz operation, 7.81 ms: during 4.19-mhz operation)
39 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) table 9-1. status of each hardware after reset (1/2) hardware reset signal generation reset signal generation in the standby mode in operation program counter (pc) m pd750064 sets the low-order 4 bits of sets the low-order 4 bits of program memorys address program memorys address 0000h to the pc11-pc8 and the 0000h to the pc11-pc8 and the contents of address 0001h to contents of address 0001h to the pc7-pc0. the pc7-pc0. m pd750066, sets the low-order 5 bits of sets the low-order 5 bits of 750068 program memorys address program memorys address 0000h to the pc12-pc8 and the 0000h to the pc12-pc8 and the contents of address 0001h to contents of address 0001h to the pc7-pc0. the pc7-pc0. psw carry flag (cy) held undefined skip flag (sk0-sk2) 0 0 interrupt status flag (ist0, ist1) 0 0 bank enable flag (mbe, rbe) sets the bit 6 of program sets the bit 6 of program memorys address 0000h to memorys address 0000h to the rbe and bit 7 to the mbe. the rbe and bit 7 to the mbe. stack pointer (sp) undefined undefined stack bank select register (sbs) 1000b 1000b data memory (ram) held undefined general-purpose register (x, a, h, l, d, e, b, c) held undefined bank select register (mbs, rbs) 0, 0 0, 0 basic interval counter (bt) undefined undefined timer/watchdog mode register (btm) 0 0 timer watchdog timer enable flag (wdtm) 00 timer/event counter (t0) 0 0 counter (t0) modulo register (tmod0) ffh ffh mode register (tm0) 0 0 toe0, tout f/f 0, 0 0, 0 timer/event counter (t1) 0 0 counter (t1) modulo register (tmod1) ffh ffh mode register (tm1) 0 0 toe1, tout f/f 0, 0 0, 0 watch timer mode register (wm) 0 0
40 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) table 9-1. status of each hardware after reset (2/2) hardware reset signal generation reset signal generation in the standby mode in operation serial interface shift register (sio) held undefined operation mode register (csim) 00 sbi control register (sbic) 0 0 clock generator, processor clock control register (pcc) 0 0 clock output system clock control register (scc) 0 0 circuit clock output mode register (clom) 0 0 sub-oscillator control register (sos) 0 0 a/d converter mode register (adm) 04h 04h sa register (sa) 7fh 7fh interrupt interrupt request flag (irq ) reset (0) reset (0) function interrupt enable flag (ie )0 0 interrupt priority selection register (ips) 00 int0, 1, 2 mode registers (im0, im1, im2) 0, 0, 0 0, 0, 0 digital port output buffer off off output latch cleared (0) cleared (0) i/o mode registers (pmga, pmgb) 0 0 pull-up resistor setting register (poga) 00 bit sequential buffer (bsb0-bsb3) held undefined
41 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 10. mask option the m pd750068 has the following mask options. ? mask option of p40 to p43 and p50 to p53 can select whether to incorporate the pull-up resistor. (1) the pull-up resistor is incorporated bit-wise. (2) the pull-up resistor is not incorporated. ? mask option of standby function can select the wait time with the reset signal. (1) 2 17 /f x (21.8 ms at f x = 6.0 mhz, 31.3 ms at f x = 4.19 mhz) (2) 2 15 /f x (5.46 ms at f x = 6.0 mhz, 7.81 ms at f x = 4.19 mhz) ? mask option of subsystem clock can select whether to enable the internal feedback resistor. (1) the internal feedback resistor is enabled (switch internal feedback resistor on/off by software). (2) the internal feedback resistor is disabled (disconnect internal feedback resistor by hardware).
42 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 11. instruction set (1) expression formats and description methods of operands the operand is described in the operand column of each instruction in accordance with the description method for the operand expression format of the instruction. for details, refer to ra75x assembler package users manuallanguage (eeu-1363) . if there are several elements, one of them is selected. capital letters and the + and C symbols are key words and are described as they are. for immediate data, appropriate numbers or labels are described. instead of the labels such as mem, fmem, pmem, and bit, the symbols of the register flags can be described. however, there are restrictions in the labels that can be described for fmem and pmem. for details, see m pd750068 users manual (u10670e) . expression description method format reg x, a, b, c, d, e, h, l reg1 x, b, c, d, e, h, l rp xa, bc, de, hl rp1 bc, de, hl rp2 bc, de rp' xa, bc, de, hl, xa', bc', de', hl' rp'1 bc, de, hl, xa', bc', de', hl' rpa hl, hl+, hlC, de, dl rpa1 de, dl n4 4-bit immediate data or label n8 8-bit immediate data or label mem 8-bit immediate data or label note bit 2-bit immediate data or label fmem fb0h-fbfh, ff0h-fffh immediate data or label pmem fc0h-fffh immediate data or label addr, addr1 0000h-0fffh immediate data or label ( m pd750064) (mk ii mode only) 0000h-17ffh immediate data or label ( m pd750066) 0000h-1fffh immediate data or label ( m pd750068) caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20h-7fh immediate data (where bit0 = 0) or label portn port0-port6, port11 ie iebt, iet0, iet1, ie0-ie2, ie4, iecsi, iew rbn rb0-rb3 mbn mb0, mb1, mb15 note mem can be only used for even address in 8-bit data processing.
43 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) (2) legend in explanation of operation a : a register; 4-bit accumulator b : b register c : c register d : d register e : e register h : h register l : l register x : x register xa : xa register pair; 8-bit accumulator bc : bc register pair de : de register pair hl : hl register pair xa : xa expanded register pair bc : bc expanded register pair de : de expanded register pair hl : hl expanded register pair pc : program counter sp : stack pointer cy : carry flag; bit accumulator psw : program status word mbe : memory bank enable flag rbe : register bank enable flag portn : port n (n = 0-6, 11) ime : interrupt master enable flag ips : interrupt priority selection register ie : interrupt enable flag rbs : register bank selection register mbs : memory bank selection register pcc : processor clock control register . : separation between address and bit ( ) : the contents addressed by h : hexadecimal data
44 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) (3) explanation of symbols under addressing area column *1 mb = mbe?mbs (mbs = 0, 1, 15) *2 mb = 0 *3 mbe = 0 : mb = 0 (000h-07fh) mb = 15 (f80h-fffh) data memory addressing mbe = 1 : mb = mbs (mbs = 0, 1, 15) *4 mb = 15, fmem = fb0h-fbfh, ff0h-fffh *5 mb = 15, pmem = fc0h-fffh *6 addr = 0000h-0fffh ( m pd750064) 0000h-17ffh ( m pd750066) 0000h-1fffh ( m pd750068) *7 addr, addr1 = (current pc) C 15 to (current pc) C 1 (current pc) + 2 to (current pc) + 16 *8 caddr = 0000h-0fffh ( m pd750064) 0000h-0fffh (pc 12 = 0: m pd750066, 750068) 1000h-17ffh (pc 12 = 1: m pd750066) program memory addressing 1000h-1fffh (pc 12 = 1: m pd750068) *9 faddr = 0000h-07ffh *10 taddr = 0020h-007fh *11 mk ii mode only addr1 = 0000h-0fffh ( m pd750064) 0000h-17ffh ( m pd750066) 0000h-1fffh ( m pd750068) remarks 1. mb indicates memory bank that can be accessed. 2. in *2, mb = 0 independently of how mbe and mbs are set. 3. in *4 and *5, mb = 15 independently of how mbe and mbs are set. 4. *6 to *11 indicate the areas that can be addressed. (4) explanation of number of machine cycles column s denotes the number of machine cycles required by skip operation when a skip instruction is executed. the value of s varies as follows. ? when no skip is made: s = 0 ? when the skipped instruction is a 1- or 2-byte instruction: s = 1 ? when the skipped instruction is a 3-byte instruction note : s = 2 note 3-byte instruction: br !addr, bra !addr1, call !addr or calla !addr1 instruction caution the geti instruction is skipped in one machine cycle. one machine cycle is equal to one cycle (= t cy ) of cpu clock f ; time can be selected from among four types by setting pcc.
45 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area transfer mov a, #n4 1 1 a n4 string effect a reg1, #n4 2 2 reg1 n4 xa, #n8 2 2 xa n8 string effect a hl, #n8 2 2 hl n8 string effect b rp2, #n8 2 2 rp2 n8 a, @hl 1 1 a (hl) *1 a, @hl+ 1 2+s a (hl), then l l+1 *1 l = 0 a, @hlC 1 2+s a (hl), then l lC1 *1 l = fh a, @rpa1 1 1 a (rpa1) *2 xa, @hl 2 2 xa (hl) *1 @hl, a 1 1 (hl) a*1 @hl, xa 2 2 (hl) xa *1 a, mem 2 2 a (mem) *3 xa, mem 2 2 xa (mem) *3 mem, a 2 2 (mem) a*3 mem, xa 2 2 (mem) xa *3 a, reg1 2 2 a reg1 xa, rp' 2 2 xa rp' reg1, a 2 2 reg1 a rp'1, xa 2 2 rp'1 xa xch a, @hl 1 1 a (hl) *1 a, @hl+ 1 2+s a (hl), then l l+1 *1 l = 0 a, @hlC 1 2+s a (hl), then l lC1 *1 l = fh a, @rpa1 1 1 a (rpa1) *2 xa, @hl 2 2 xa (hl) *1 a, mem 2 2 a (mem) *3 xa, mem 2 2 xa (mem) *3 a, reg1 1 1 a reg1 xa, rp' 2 2 xa rp'
m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 46 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area table movt xa, @pcde 1 3 m pd750064 reference xa (pc 11C8 +de) rom m pd750066, 750068 xa (pc 12C8 +de) rom xa, @pcxa 1 3 m pd750064 xa (pc 11C8 +xa) rom m pd750066, 750068 xa (pc 12C8 +xa) rom xa, @bcde 1 3 xa (bcde) rom note *6 xa, @bcxa 1 3 xa (bcxa) rom note *6 bit transfer mov1 cy, fmem.bit 2 2 cy (fmem.bit) *4 cy, pmem.@l 2 2 cy (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy (h+mem 3C0 .bit) *1 fmem.bit, cy 2 2 (fmem.bit) cy *4 pmem.@l, cy 2 2 (pmem 7C2 +l 3C2 .bit(l 1C0 )) cy *5 @h+mem.bit, cy 2 2 (h+mem 3C0 .bit) cy *1 operation adds a, #n4 1 1+s a a+n4 carry xa, #n8 2 2+s xa xa+n8 carry a, @hl 1 1+s a a+(hl) *1 carry xa, rp' 2 2+s xa xa+rp' carry rp'1, xa 2 2+s rp'1 rp'1+xa carry addc a, @hl 1 1 a, cy a+(hl)+cy *1 xa, rp' 2 2 xa, cy xa+rp'+cy rp'1, xa 2 2 rp'1, cy rp'1+xa+cy subs a, @hl 1 1+s a aC(hl) *1 borrow xa, rp' 2 2+s xa xaCrp' borrow rp'1, xa 2 2+s rp'1 rp'1Cxa borrow subc a, @hl 1 1 a, cy aC(hl)Ccy *1 xa, rp' 2 2 xa, cy xaCrp'Ccy rp'1, xa 2 2 rp'1, cy rp'1CxaCcy note set 0 to register b if the m pd750064 is used. only low-order one bit of register b will be valid if the m pd750066, 750068 is used.
47 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area operation and a, #n4 2 2 a a ? n4 a, @hl 1 1 a a ? (hl) *1 xa, rp' 2 2 xa xa ? rp' rp'1, xa 2 2 rp'1 rp'1 ? xa or a, #n4 2 2 a a | n4 a, @hl 1 1 a a | (hl) *1 xa, rp' 2 2 xa xa | rp' rp'1, xa 2 2 rp'1 rp'1 | xa xor a, #n4 2 2 a a v n4 a, @hl 1 1 a a v (hl) *1 xa, rp' 2 2 xa xa v rp' rp'1, xa 2 2 rp'1 rp'1 v xa accumulator rorc a 1 1 cy a 0 , a 3 cy, a nC1 a n manipulation not a 2 2 a a increment incs reg 1 1+s reg reg+1 reg = 0 and decrement rp1 1 1+s rp1 rp1+1 rp1 = 00h @hl 2 2+s (hl) (hl)+1 *1 (hl) = 0 mem 2 2+s (mem) (mem)+1 *3 (mem) = 0 decs reg 1 1+s reg regC1 reg = fh rp' 2 2+s rp' rp'C1 rp' = ffh comparison ske reg, #n4 2 2+s skip if reg = n4 reg = n4 @hl, #n4 2 2+s skip if (hl) = n4 *1 (hl) = n4 a, @hl 1 1+s skip if a = (hl) *1 a = (hl) xa, @hl 2 2+s skip if xa = (hl) *1 xa = (hl) a, reg 2 2+s skip if a = reg a = reg xa, rp' 2 2+s skip if xa = rp' xa = rp' carry flag set1 cy 1 1 cy 1 manipulation clr1 cy 1 1 cy 0 skt cy 1 1+s skip if cy = 1 cy = 1 not1 cy 1 1 cy cy
m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 48 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area memory bit set1 mem.bit 2 2 (mem.bit) 1*3 manipulation fmem.bit 2 2 (fmem.bit) 1*4 pmem.@l 2 2 (pmem 7C2 +l 3C2 .bit(l 1C0 )) 1*5 @h+mem.bit 2 2 (h+mem 3C0 .bit) 1*1 clr1 mem.bit 2 2 (mem.bit) 0*3 fmem.bit 2 2 (fmem.bit) 0*4 pmem.@l 2 2 (pmem 7C2 +l 3C2 .bit(l 1C0 )) 0*5 @h+mem.bit 2 2 (h+mem 3C0 .bit) 0*1 skt mem.bit 2 2+s skip if (mem.bit)=1 *3 (mem.bit)=1 fmem.bit 2 2+s skip if (fmem.bit)=1 *4 (fmem.bit)=1 pmem.@l 2 2+s skip if (pmem 7C2 +l 3C2 .bit(l 1C0 ))=1 *5 (pmem.@l)=1 @h+mem.bit 2 2+s skip if (h+mem 3C0 .bit)=1 *1 (@h+mem.bit)=1 skf mem.bit 2 2+s skip if (mem.bit)=0 *3 (mem.bit)=0 fmem.bit 2 2+s skip if (fmem.bit)=0 *4 (fmem.bit)=0 pmem.@l 2 2+s skip if (pmem 7C2 +l 3C2 .bit(l 1C0 ))=0 *5 (pmem.@l)=0 @h+mem.bit 2 2+s skip if (h+mem 3C0 .bit)=0 *1 (@h+mem.bit)=0 sktclr fmem.bit 2 2+s skip if (fmem.bit)=1 and clear *4 (fmem.bit)=1 pmem.@l 2 2+s skip if (pmem 7C2 +l 3C2 .bit(l 1C0 ))=1 and clear *5 (pmem.@l)=1 @h+mem.bit 2 2+s skip if (h+mem 3C0 .bit)=1 and clear *1 (@h+mem.bit)=1 and1 cy, fmem.bit 2 2 cy cy ? (fmem.bit) *4 cy, pmem.@l 2 2 cy cy ? (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy cy ? (h+mem 3C0 .bit) *1 or1 cy, fmem.bit 2 2 cy cy | (fmem.bit) *4 cy, pmem.@l 2 2 cy cy | (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy cy | (h+mem 3C0 .bit) *1 xor1 cy, fmem.bit 2 2 cy cy v (fmem.bit) *4 cy, pmem.@l 2 2 cy cy v (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy cy v (h+mem 3C0 .bit) *1
49 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area branch br note addr C C m pd750064 *6 pc 11C0 addr select appropriate instruction from among br !addr, brcb !caddr and br $addr according to the assembler being used. m pd750066, 750068 pc 12C0 addr select appropriate instruction from among br !addr, brcb !caddr and br $addr according to the assembler being used. addr1 C C m pd750064 *11 pc 11-0 addr1 select appropriate instruction from among br !addr, bra !addr1, brcb !caddr and br $addr1 according to the assembler being used. m pd750066, 750068 pc 12C0 addr1 select appropriate instruction from among br !addr, bra !addr1, brcb !caddr and br $addr1 according to the assembler being used. ! addr 3 3 m pd750064 *6 pc 11C0 addr m pd750066, 750068 pc 12C0 addr $addr 1 2 m pd750064 *7 pc 11C0 addr m pd750066, 750068 pc 12C0 addr $addr1 1 2 m pd750064 pc 11C0 addr1 m pd750066, 750068 pc 12C0 addr1 note the operations indicated with thick lines can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode.
m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 50 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area branch br pcde 2 3 m pd750064 pc 11C0 pc 11-8 +de m pd750066, 750068 pc 12C0 pc 12-8 +de pcxa 2 3 m pd750064 pc 11C0 pc 11-8 +xa m pd750066, 750068 pc 12C0 pc 12-8 +xa bcde 2 3 m pd750064 *6 pc 11C0 bcde note 1 m pd750066, 750068 pc 12C0 bcde note 2 bcxa 2 3 m pd750064 *6 pc 11C0 bcxa note 1 m pd750066, 750068 pc 12C0 bcxa note 2 bra note 3 33 m pd750064 *11 pc 11C0 addr1 m pd750066, 750068 pc 12C0 addr1 brcb !caddr 2 2 m pd750064 *8 pc 11C0 caddr 11C0 m pd750066, 750068 pc 12C0 pc 12 +caddr 11C0 subroutine calla note 3 33 m pd750064 *11 stack control (spC2) , , mbe, rbe (spC6) (spC3) (spC4) pc 11C0 (spC5) 0, 0, 0, 0 pc 11C0 addr1, sp spC6 m pd750066, 750068 (spC2) , , mbe, rbe (spC6) (spC3) (spC4) pc 11C0 (spC5) 0, 0, 0, pc 12 pc 12C0 addr1, sp spC6 notes 1. 0 must be set to b register. 2. only low-order one bit is valid in b register. 3. the operations indicated with thick lines can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode.
51 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area subroutine call note !addr 3 3 m pd750064 *6 stack control (spC3) mbe, rbe, 0, 0 (spC4) (spC1) (spC2) pc 11C0 pc 11C0 addr, sp spC4 m pd750066, 750068 (spC3) mbe, rbe, 0, pc 12 (spC4) (spC1) (spC2) pc 11C0 pc 12C0 addr, sp spC4 4 m pd750064 (spC2) , , mbe, rbe (spC6) (spC3) (spC4) pc 11C0 (spC5) 0, 0, 0, 0 pc 11C0 addr, sp spC6 m pd750066, 750068 (spC2) , , mbe, rbe (spC6) (spC3) (spC4) pc 11C0 (spC5) 0, 0, 0, pc 12 pc 12C0 addr, sp spC6 callf note !faddr 2 2 m pd750064 *9 (spC3) mbe, rbe, 0, 0 (spC4) (spC1) (spC2) pc 11C0 pc 11C0 0+faddr, sp spC4 m pd750066, 750068 (spC3) mbe, rbe, 0, pc 12 (spC4) (spC1) (spC2) pc 11C0 pc 12C0 00+faddr, sp spC4 3 m pd750064 (spC2) , , mbe, rbe (spC6) (spC3) (spC4) pc 11C0 (spC5) 0, 0, 0, 0 pc 11C0 0+faddr, sp spC6 m pd750066, 750068 (spC2) , , mbe, rbe (spC6) (spC3) (spC4) pc 11C0 (spC5) 0, 0, 0, pc 12 pc 12C0 00+faddr, sp spC6 note the operations indicated with thick lines can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode.
m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 52 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area subroutine ret note 13 m pd750064 stack control pc 11C0 (sp) (sp+3) (sp+2) mbe, rbe, 0, 0 (sp+1), sp sp+4 m pd750066, 750068 pc 11C0 (sp) (sp+3) (sp+2) mbe, rbe, 0, pc 12 (sp+1), sp sp+4 m pd750064 , , mbe, rbe (sp+4) 0, 0, 0, 0, (sp+1) pc 11C0 (sp) (sp+3) (sp+2), sp sp+6 m pd750066, 750068 , , mbe, rbe (sp+4) mbe, 0, 0, pc 12 (sp+1) pc 11C0 (sp) (sp+3) (sp+2), sp sp+6 rets note 13+s m pd750064 unconditional mbe, rbe, 0, 0 (sp+1) pc 11C0 (sp) (sp+3) (sp+2) sp sp+4 then skip unconditionally m pd750066, 750068 mbe, rbe, 0, pc 12 (sp+1) pc 11C0 (sp) (sp+3) (sp+2) sp sp+4 then skip unconditionally m pd750064 0, 0, 0, 0 (sp+1) pc 11C0 (sp) (sp+3) (sp+2) , , mbe, rbe (sp+4) sp sp+6 then skip unconditionally m pd750066, 750068 0, 0, 0, pc 12 (sp+1) pc 11C0 (sp) (sp+3) (sp+2) , , mbe, rbe (sp+4) sp sp+4 then skip unconditionally note the operations indicated with thick lines can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode.
53 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area subroutine reti note 1 13 m pd750064 stack control mbe, rbe, 0, 0 (sp+1) pc 11C0 (sp) (sp+3) (sp+2) psw (sp+4) (sp+5), sp sp+6 m pd750066, 750068 mbe, rbe, 0, pc 12 (sp+1) pc 11C0 (sp) (sp+3) (sp+2) psw (sp+4) (sp+5), sp sp+6 m pd750064 0, 0, 0, 0 (sp+1) pc 11C0 (sp) (sp+3) (sp+2) psw (sp+4) (sp+5), sp sp+6 m pd750066, 750068 0, 0, 0, pc 12 (sp+1) pc 11C0 (sp) (sp+3) (sp+2) psw (sp+4) (sp+5), sp sp+6 push rp 1 1 (spC1)(spC2) rp, sp spC2 bs 2 2 (spC1) mbs, (spC2) rbs, sp spC2 pop rp 1 1 rp (sp+1) (sp), sp sp+2 bs 2 2 mbs (sp+1), rbs (sp), sp sp+2 interrupt ei 2 2 ime (ips.3) 1 control ie 22ie 1 di 2 2 ime (ips.3) 0 ie 22ie 0 input/output in note 2 a, portn 2 2 a portn (n = 0-6, 11) xa, portn 2 2 xa portn+1, portn (n = 4) out note 2 portn, a 2 2 portn a (n = 2-6) portn, xa 2 2 portn+1, portn xa (n = 4) cpu control halt 2 2 set halt mode (pcc.2 1) stop 2 2 set stop mode (pcc.3 1) nop 1 1 no operation special sel rbn 2 2 rbs n (n = 0-3) mbn 2 2 mbs n (n = 0, 1, 15) notes 1. the operations indicated with thick lines can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode. 2. while the in instruction and out instruction are being executed, the mbe must be set to 0 or 1, and mbs must be set to 15.
m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 54 instruction number number addressing mnemonic operand of machine operation skip condition group of bytes cycles area special geti notes 1, 2 taddr 1 3 m pd750064 *10 ? when tbr instruction pc 11C0 (taddr) 3C0 + (taddr+1) ? when tcall instruction (spC4) (spC1) (spC2) pc 11C0 (spC3) mbe, rbe, 0, 0 pc 11C0 (taddr) 3C0 + (taddr+1) sp spC4 ? when instruction other than tbr and depending on tcall instructions the reference (taddr) (taddr+1) instruction is executed. instruction m pd750066, 750068 ? when tbr instruction pc 12C0 (taddr) 4C0 + (taddr+1) ? when tcall instruction (spC4) (spC1) (spC2) pc 11C0 (spC3) mbe, rbe, 0, pc 12 pc 12C0 (taddr) 4C0 + (taddr+1) sp spC4 ? when instruction other than tbr and depending on tcall instructions the reference (taddr) (taddr+1) instruction is executed. instruction 3 m pd750064 *10 ? when tbr instruction pc 11C0 (taddr) 3C0 + (taddr+1) 4 ? when tcall instruction (spC6) (spC3) (spC4) pc 11C0 (spC5) 0, 0, 0, 0 (spC2) , , mbe, rbe pc 11C0 (taddr) 3C0 + (taddr+1) sp spC6 3 ? when instruction other than tbr and depending on tcall instructions the reference (taddr) (taddr+1) instruction is executed. instruction 3 m pd750066, 750068 ? when tbr instruction pc 12C0 (taddr) 4C0 + (taddr+1) 4 ? when tcall instruction (spC6) (spC3) (spC4) pc 11C0 (spC5) 0, 0, 0, pc 12 (spC2) , , mbe, rbe pc 12C0 (taddr) 4C0 + (taddr+1) sp spC6 3 ? when instruction other than tbr and depending on tcall instructions the reference (taddr) (taddr+1) instruction is executed. instruction notes 1. the tbr and tcall instructions are the table definition assembler pseudo instructions of the geti instruction. 2. the operations indicated with thick lines can be performed only in the mk ii mode. the other operations can be performed only in the mk i mode. C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
55 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) ports 4, 5 12. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd C0.3 to +7.0 v input voltage v i1 other than ports 4, 5 C0.3 to v dd +0.3 v v i2 pull-up resistor provided C0.3 to v dd +0.3 v n-ch open drain C0.3 to +14 v output voltage v o C0.3 to v dd +0.3 v high-level output current i oh per pin C10 ma total of all pins C30 ma low-level output current i ol per pin 30 ma total of all pins 220 ma operating ambient t a C40 to +85 c temperature storage temperature t stg C65 to +150 c caution if the absolute maximum rating of even one of the parameters is exceeded even momentarily, the quality of the product may be degraded. the absolute maximum ratings are therefore values which, when exceeded, can cause the product to be damaged. be sure that these values are never exceeded when using the product. capacitance (t a = 25 c, v dd = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c in f = 1 mhz 15 pf output capacitance c out unmeasured pins returned to 0 v 15 pf i/o capacitance c io 15 pf
m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 56 main system clock oscillation circuit characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended parameter conditions min. typ. max. unit constants ceramic oscillation frequency 1.0 6.0 note 2 mhz resonator (f x ) note 1 oscillation after v dd has 4 ms stabilization time note 3 reached min. value of oscillation voltage range crystal oscillation frequency 1.0 6.0 note 2 mhz resonator (f x ) note 1 oscillation v dd = 4.5 to 5.5 v 10 ms stabilization time note 3 30 external x1 input frequency 1.0 6.0 note 2 mhz clock (f x ) note 1 x1 input high-, 83.3 500 ns low-level widths (t xh , t xl ) notes 1. the oscillation frequency and x1 input frequency shown above indicate characteristics of the oscillation circuit only. for the instruction execution time, refer to ac characteristics. 2. if the oscillation frequency is 4.19 mhz < f x - 6.0 mhz at 1.8 v - v dd < 2.7 v, do not select the processor clock control register (pcc) = 0011. if pcc = 0011, one machine cycle time is less than 0.95 m s, falling short of the rated value of 0.95 m s. 3. the oscillation stabilization time is the time required for oscillation to be stabilized after v dd has been applied or stop mode has been released. caution when using the main system clock oscillation circuit, wire the portion enclosed in the dotted line in the above figure as follows to prevent adverse influence due to wiring capacitance: ? keep the wiring length as short as possible. ? do not cross the wiring with other signal lines. ? do not route the wiring in the vicinity of a line through which a high alternating current flows. ? always keep the ground point of the capacitor of the oscillation circuit at the same potential as v ss . ? do not ground to a ground pattern through which a high current flows. ? do not extract signals from the oscillation circuit. x1 x2 x1 x2 c1 c2 x1 x2 c1 c2
57 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) xt1 xt2 subsystem clock oscillation circuit characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended parameter conditions min. typ. max. unit constants crystal oscillation frequency 32 32.768 35 khz resonator (f xt ) note 1 oscillation v dd = 4.5 to 5.5 v 1.0 2 s stabilization time note 2 10 external xt1 input frequency 32 100 khz clock (f xt ) note 1 xt1 input high-, 5 15 m s low-level widths (t xth , t xtl ) notes 1. the oscillation frequency and xt1 input frequency shown above indicate characteristics of the oscillation circuit only. for the instruction execution time, refer to ac characteristics. 2. the oscillation stabilization time is the time required for oscillation to be stabilized after v dd has been applied. caution when using the subsystem clock oscillation circuit, wire the portion enclosed in the dotted line in the above figure as follows to prevent adverse influence due to wiring capacitance: ? keep the wiring length as short as possible. ? do not cross the wiring with other signal lines. ? do not route the wiring in the vicinity of a line through which a high alternating current flows. ? always keep the ground point of the capacitor of the oscillation circuit at the same potential as v ss . ? do not ground to a ground pattern through which a high current flows. ? do not extract signals from the oscillation circuit. the subsystem clock oscillation circuit has a low amplification factor to reduce current dissipation and is more susceptible to noise than the main system clock oscillation circuit. therefore, exercise utmost care in wiring the subsystem clock oscillation circuit. xt1 xt2 c3 c4 r
m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 58 recommended oscillation circuit constants ceramic resonator (t a = C40 to +85 c) oscillation oscillation manufacturer part number frequency circuit constant voltage range remarks (mhz) (pf) (v dd ) c1 c2 min. max. murata mfg. csb1000j note 1.0 100 100 2.0 5.5 rd = 1 k w co., ltd. csa2.00mg040 2.0 100 100 2.3 C cst2.00mg040 C C capacitor-contained model csa4.19mg 4.19 30 30 1.9 C cst4.19mgw C C capacitor-contained model csa4.19mgu 30 30 1.8 C cst4.19mgwu C C capacitor-contained model csa6.00mg 6.0 30 30 3.0 C cst6.00mgw C C capacitor-contained model csa6.00mgu 30 30 2.4 C cst6.00mgwu C C capacitor-contained model kyocera corp. kbr-1000f/y 1.0 100 100 1.8 5.5 C kbr-2.0ms 2.0 68 68 1.95 kbr-4.19msa 4.19 33 33 1.8 kbr-6.0msa 6.0 33 33 tdk ccr1000k2 1.0 100 100 1.8 5.5 C ccr2.0mc33 2.0 C C 2.0 capacitor-contained model ccr4.19mc3 4.19 fcr4.19mc5 2.2 ccr6.0mc3 6.0 2.0 fcr6.0mc5 2.2 note when using the csb1000j (1.0 mhz) by murata mfg. co., ltd. as a ceramic resonator, a limiting resistor (rd = 1 k w ) is necessary (refer to the figure below). the limiting resistor is not necessary when using the other recommended resonators. caution the oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee accuracy of the oscillation frequency. if the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. for this, it is necessary to directly contact the manufacturer of the resonator being used. x1 x2 c1 c2 rd csb1000j
59 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) dc characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit low-level output i ol per pin 15 ma current total of all pins 150 ma high-level input v ih1 ports 2, 3, 11 2.7 v - v dd - 5.5 v 0.7 v dd v dd v voltage 1.8 v - v dd < 2.7 v 0.9 v dd v dd v v ih2 ports 0, 1, 6, reset 2.7 v - v dd - 5.5 v 0.8 v dd v dd v 1.8 v - v dd < 2.7 v 0.9 v dd v dd v v ih3 ports 4, 5 pull-up resistor 2.7 v - v dd - 5.5 v 0.7 v dd v dd v provided 1.8 v - v dd < 2.7 v 0.9 v dd v dd v n-ch open drain 2.7 v - v dd - 5.5 v 0.7 v dd 13 v 1.8 v - v dd < 2.7 v 0.9 v dd 13 v v ih4 x1, xt1 v dd C0.1 v dd v low-level input v il1 ports 2, 3, 4, 5, 11 2.7 v - v dd - 5.5 v 0 0.3 v dd v voltage 1.8 v - v dd < 2.7 v 0 0.1 v dd v v il2 ports 0, 1, 6, reset 2.7 v - v dd - 5.5 v 0 0.2 v dd v 1.8 v - v dd < 2.7 v 0 0.1 v dd v v il3 x1, xt1 0 0.1 v high-level output v oh sck, so, ports 2, 3, 6 i oh = C1.0 ma v dd C0.5 v voltage low-level output v ol1 sck, so, ports 2, 3, 4, 5, 6 i ol = 15 ma 0.2 2.0 v voltage v dd = 4.5 to 5.5 v i ol = 1.6 ma 0.4 v v ol2 sb0, sb1 n-ch open drain 0.2 v dd v pull-up resistor ? 1 k w high-level input i lih1 v in = v dd pins other than x1, xt1 3 m a leakage current i lih2 x1, xt1 20 m a i lih3 v in = 13 v ports 4, 5 (n-ch open drain) 20 m a low-level input i lil1 v in = 0 v pins other than ports 4, 5, x1, xt1 C3 m a leakage current i lil2 x1, xt1 C20 m a i lil3 ports 4, 5 (n-ch open drain) C3 m a when input instruction is not executed C30 m a v dd = 5.0 v C10 C27 m a v dd = 3.0 v C3 C8 m a high-level output i loh1 v out = v dd sck, so/sb0, sb1, ports 2, 3, 6, 3 m a leakage current ports 4, 5 (pull-up resistor provided) i loh2 v out = 13 v ports 4, 5 (n-ch open drain) 20 m a low-level output i lol v out = 0 v C3 m a leakage current internal pull-up r l1 v in = 0 v ports 0, 1, 2, 3, 6 (except pin p00) 50 100 200 k w resistor r l2 ports 4, 5 15 30 60 k w ports 4, 5 (n-ch open drain) when input instruc- tion is executed
m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 60 dc characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit supply current note 1 i dd1 v dd = 5.0 v 10 % note 3 2.2 6.6 ma v dd = 3.0 v 10 % note 4 0.48 1.5 ma i dd2 halt v dd = 5.0 v 10 % 0.86 2.6 ma mode v dd = 3.0 v 10 % 0.43 1.3 ma i dd1 v dd = 5.0 v 10 % note 3 1.7 4.5 ma v dd = 3.0 v 10 % note 4 0.4 1.2 ma i dd2 halt v dd = 5.0 v 10 % 0.7 2 ma mode v dd = 3.0 v 10 % 0.39 1.2 ma i dd3 low- v dd = 3.0 v 10 % 11 33 m a voltage v dd = 2.0 v 10 % 5.5 17 m a mode note 6 v dd = 3.0 v, t a = 25 c 11 22 m a v dd = 3.0 v 10 % 9.2 27 m a v dd = 3.0 v, t a = 25 c 9.2 18 m a i dd4 halt low- v dd = 3.0 v 10 % 6.4 20 m a mode voltage v dd = 2.0 v 10 % 2.5 8 m a mode note 6 v dd = 3.0 v, t a = 25 c 6.4 12.8 m a v dd = 3.0 v 10 % 4.6 13.8 m a v dd = 3.0 v, t a = 25 c 4.6 9.2 m a i dd5 xt1 = v dd = 5.0 v 10 % 0.05 10 m a 0 v note 8 v dd = 3.0 v 10 % 0.02 5 m a stop mode t a = 25 c 0.02 3 m a notes 1. the current flowing through the internal pull-up resistor is not included. 2. including the case when the subsystem clock oscillates. 3. when the device operates in high-speed mode with the processor clock control register (pcc) set to 0011. 4. when the device operates in low-speed mode with pcc set to 0000. 5. when the device operates on the subsystem clock, with the system clock control register (scc) set to 1001 and oscillation of the main system clock stopped. 6. when the sub-oscillation circuit control register (sos) is set to 0000. 7. when sos is set to 0010. 8. when sos is set to 00 1, and the sub-oscillation circuit feedback resistor is not used ( : dont care). 6.0 mhz note 2 crystal oscillation c1 = c2 = 22 pf 4.19 mhz note 2 crystal oscillation c1 = c2 = 22 pf 32.768 khz note 5 crystal oscillation low current dissipation mode note 7 low current dissipation mode note 7
61 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) ac characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit cpu clock cycle time note 1 t cy operates with v dd = 2.7 to 5.5 v 0.67 64 m s (minimum instruction main system clock 0.95 64 m s execution time = 1 operates with 114 122 125 m s machine cycle) subsystem clock ti0, ti1 input frequency f ti v dd = 2.7 to 5.5 v 0 1.0 mhz 0 275 khz ti0, ti1 input high-, low-level t tih , t til v dd = 2.7 to 5.5 v 0.48 m s widths 1.8 m s interrupt input high-, t inth , t intl int0 im02 = 0 note 2 m s low-level widths im02 = 1 10 m s int1, 2, 4 10 m s kr0-3 10 m s reset low-level width t rsl 10 m s notes 1. the cycle time (minimum instruction execution time) of the cpu clock ( f ) is determined by the oscillation frequency of the connected resonator (and external clock), the system clock control register (scc), and processor clock control register (pcc). the figure on the right shows the supply voltage v dd vs. cycle time t cy characteristics when the device operates with the main system clock. 2. 2t cy or 128/f x depending on the setting of the interrupt mode register (im0). 0 1 2 3 4 5 6 1 0.5 2 3 4 5 6 60 64 (with main system clock) t cy vs v dd operation guaranteed range cycle time t cy [ s] m supply voltage v dd [v]
m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 62 note 2 note 2 serial transfer operation 2-wire and 3-wire serial i/o modes (sck internal clock output): (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit sck cycle time t kcy1 v dd = 2.7 to 5.5 v 1300 ns 3800 ns sck high-, low-level widths t kl1 ,v dd = 2.7 to 5.5 v t kcy1 /2C50 ns t kh1 t kcy1 /2C150 ns si note 1 setup time (to sck ? )t sik1 v dd = 2.7 to 5.5 v 150 ns 500 ns si note 1 hold time t ksi1 v dd = 2.7 to 5.5 v 400 ns (from sck ? ) 600 ns sck ? ? so note 1 output t kso1 r l = 1 k w ,v dd = 2.7 to 5.5 v 0 250 ns delay time c l = 100 pf 0 1000 ns notes 1. read as sb0 or sb1 when using the 2-wire serial i/o mode. 2. r l and c l respectively indicate the load resistance and load capacitance of the so output line. 2-wire and 3-wire serial i/o modes (sck external clock input): (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit sck cycle time t kcy2 v dd = 2.7 to 5.5 v 800 ns 3200 ns sck high-, low-level widths t kl2 ,v dd = 2.7 to 5.5 v 400 ns t kh2 1600 ns si note 1 setup time (to sck ? )t sik2 v dd = 2.7 to 5.5 v 100 ns 150 ns si note 1 hold time t ksi2 v dd = 2.7 to 5.5 v 400 ns (from sck ? ) 600 ns sck ? ? so note 1 output t kso2 r l = 1 k w ,v dd = 2.7 to 5.5 v 0 300 ns delay time c l = 100 pf 0 1000 ns notes 1. read as sb0 or sb1 when using the 2-wire serial i/o mode. 2. r l and c l respectively indicate the load resistance and load capacitance of the so output line.
63 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) a/d converter characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v, 1.8 v - av ref - v dd ) parameter symbol conditions min. typ. max. unit resolution 888bit absolute accuracy note 1 v dd = av ref 2.7 v - v dd 1.5 lsb 1.8 v - v dd < 2.7 v 3 lsb v dd ? av ref 3 lsb conversion time t conv note 2 168/f x m s sampling time t samp note 3 44/f x m s analog input voltage v ian av ss av ref v analog input impedance r an 1000 m w av ref current i ref 0.25 2.0 ma notes 1. absolute accuracy excluding quantization error (1/2lsb) 2. time until end of conversion (eoc = 1) after execution of conversion start instruction (40.1 m s: f x = 4.19 mhz). 3. time until end of sampling after execution of conversion start instruction (10.5 m s: f x = 4.19 mhz).
m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 64 ac timing test points (except x1 and xt1 inputs) clock timing ti0, ti1 timing v ih (min.) v il (max.) v ih (min.) v il (max.) v oh (min.) v ol (max.) v oh (min.) v ol (max.) 1/f xt t xtl t xth v dd ?0.1 v 0.1 v xt1 input 1/f x t xl t xh v dd ?0.1 v 0.1 v x1 input 1/f ti t til t tih ti0, ti1
65 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) serial transfer timing 3-wire serial i/o mode 2-wire serial i/o mode t kcy1, 2 t kl1, 2 t kh1, 2 sck output data so input data si t sik1, 2 t ksi1, 2 t kso1, 2 t kcy1, 2 t kl1, 2 t kh1, 2 sck sb0, 1 t sik1, 2 t ksi1, 2 t kso1, 2
m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 66 interrupt input timing reset input timing int0, 1, 2, 4 kr0-3 t intl t inth reset t rsl
67 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) data retention characteristics of data memory in stop mode and at low supply voltage (t a = C40 to +85 c) parameter symbol conditions min. typ. max. unit release signal setup time t srel 0 m s oscillation stabilization t wait released by reset note 2 ms wait time note 1 released by interrupt request note 3 ms notes 1. the oscillation stabilization wait time is the time during which the cpu stops operating to prevent unstable operation when oscillation is started. 2. either 2 17 /f x or 2 15 /f x can be selected by mask option. 3. set by the basic interval timer mode register (btm). (refer to the table below.) btm3 btm2 btm1 btm0 wait time f x = 4.19 mhz f x = 6.0 mhz C0002 20 /f x (approx. 250 ms) 2 20 /f x (approx. 175 ms) C0112 17 /f x (approx. 31.3 ms) 2 17 /f x (approx. 21.8 ms) C1012 15 /f x (approx. 7.81 ms) 2 15 /f x (approx. 5.46 ms) C1112 13 /f x (approx. 1.95 ms) 2 13 /f x (approx. 1.37 ms) data retention timing (when stop mode released by reset) data retention timing (standby release signal: when stop mode released by interrupt signal) stop mode data retention mode internal reset operation operation mode stop instruction execution halt mode v dd reset v dddr t wait t srel stop mode data retention mode operation mode halt mode t srel v dddr t wait stop instruction execution v dd standby release signal (interrupt request)
m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 68 13. characteristic curves (for referecnce only) i dd vs v dd (main system clock: 6.0-mhz crystal resonator) 10 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 012345678 pcc = 0011 pcc = 0010 pcc = 0001 xt1 xt2 x1 x2 6.0 mhz 32.768 khz 330 k w 22 pf 22 pf 33 pf 33 pf supply current i dd (ma) main system clock halt mode + 32-khz oscillation subsystem clock operation mode (sos.1 = 0) subsystem clock halt mode (sos.1 = 0) and main system clock stop mode + 32-khz oscillation (sos.1 = 0) crystal resonator crystal resonator supply voltage v dd (v) (t a = 25 ?c) pcc = 0000 subsystem clock halt mode (sos.1 = 1) and main system clock stop mode + 32-khz oscillation (sos.1 = 1)
69 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) i dd vs v dd (main system clock: 4.19-mhz crystal resonator) 10 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 012345678 pcc = 0011 pcc = 0010 pcc = 0001 xt1 xt2 x1 x2 4.19 mhz 32.768 khz 330 k w 22 pf 22 pf 33 pf 33 pf supply current i dd (ma) main system clock halt mode + 32-khz oscillation subsystem clock operation mode (sos.1 = 0) subsystem clock halt mode (sos.1 = 0) and main system clock stop mode + 32-khz oscillation (sos.1 = 0) crystal resonator crystal resonator supply voltage v dd (v) (t a = 25 ?c) pcc = 0000 subsystem clock halt mode (sos.1 = 1) and main system clock stop mode + 32-khz oscillation (sos.1 = 1)
m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 70 14. package drawings 42 pin plastic shrink dip (600 mil) item millimeters inches a b c f g h i j k 39.13 max. 1.778 (t.p.) 3.20.3 0.51 min. 4.31 max. 1.78 max. 0.17 15.24 (t.p.) 5.08 max. n 0.9 min. r 1.541 max. 0.070 max. 0.035 min. 0.1260.012 0.020 min. 0.170 max. 0.200 max. 0.600 (t.p.) 0.007 0.070 (t.p.) p42c-70-600a-1 a c d g notes 1) each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. d 0.500.10 0.020 m 0.25 0.010 +0.10 ?.05 0~15 0~15 +0.004 ?.003 +0.004 ?.005 m k n l 13.2 0.520 2) item ??to center of leads when formed parallel. 42 1 22 21 l m r b f h j i
71 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 42 pin plastic shrink sop (375 mil) 121 a 42 22 detail of lead end c m m n b d e f g i j h k l 3 +7 ? s42gt-80-375b-1 item millimeters inches a b c d f g h i j k l 18.16 max. 0.8 (t.p.) 2.9 max. 2.5 0.2 10.3 0.3 1.13 max. 0.715 max. 0.005 0.003 0.115 max. 0.406 0.281 0.044 max. note m n 0.10 0.8 0.2 1.6 0.2 7.15 0.2 0.004 0.031 +0.009 ?.008 each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. 0.063 0.008 0.098 0.031 (t.p.) 0.15 0.006 0.10 0.004 0.014 0.35 0.125 0.075 +0.004 ?.002 +0.009 ?.008 +0.10 ?.05 +0.004 ?.003 e +0.012 ?.013 +0.009 ?.008 +0.10 ?.05
m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 72 15. recommended soldering conditions solder the m pd750068 under the following recommended conditions. for the details on the recommended soldering conditions, refer to information document semiconductor device mounting technology manual (c10535e) . for the soldering methods and conditions other than those recommended, consult nec. table 15-1. soldering conditions of surface mount type m m m m m pd750064gt- : 42-pin plastic shrink sop (375 mil, 0.8 mm pitch) m m m m m pd750066gt- : 42-pin plastic shrink sop (375 mil, 0.8 mm pitch) m m m m m pd750068gt- : 42-pin plastic shrink sop (375 mil, 0.8 mm pitch) m m m m m pd750064gt(a)- : 42-pin plastic shrink sop (375 mil, 0.8 mm pitch) m m m m m pd750066gt(a)- : 42-pin plastic shrink sop (375 mil, 0.8 mm pitch) m m m m m pd750068gt(a)- : 42-pin plastic shrink sop (375 mil, 0.8 mm pitch) soldering method soldering conditions symbol infrared reflow package peak temperature: 235 c, reflow time: 30 seconds or below ir35-00-2 (210 c or higher), number of reflow processes: 2 max. vps package peak temperature: 215 c, reflow time: 40 seconds or below vp15-00-2 (200 c or higher), number of reflow processes: 2 max. wave soldering solder temperature: 260 c or below, flow time: 10 seconds or below, ws60-00-1 number of flow processes: 1 preheating temperature: 120 c or below (package surface temperature) pin partial heating pin temperature: 300 c or below, time: 3 seconds or below (per side of device) caution do not use two or more soldering methods in combination (except the pin partial heating method). table 15-2. soldering conditions of through hole type m m m m m pd750064cu- : 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) m m m m m pd750066cu- : 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) m m m m m pd750068cu- : 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) m m m m m pd750064cu(a)- : 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) m m m m m pd750066cu(a)- : 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) m m m m m pd750068cu(a)- : 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) soldering method soldering conditions wave soldering (pin only) solder temperature: 260 c or below, flow time: 10 seconds or below pin partial heating pin temperature: 300 c or below, time: 3 seconds or below (per pin) caution in wave soldering, apply solder only to the pins. care must be taken that jet solder does not come in contact with the main body of the package.
73 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) appendix a. m m m m m pd75068, 750068 and 75p0076 functional list parameter m pd75068 m pd750068 m pd75p0076 program memory mask rom mask rom one-time prom 0000h-1f7fh 0000h-1fffh 0000h-3fffh (8064 8 bits) (8192 8 bits) (16384 8 bits) data memory 000h-1ffh (512 4 bits) cpu 75x standard cpu 75xl cpu general-purpose register 4 bits 8 or 8 bits 4 (4 bits 8 or 8 bits 4) 4 banks instruction when main system 0.95, 1.91, 15.3 m s ? 0.67, 1.33, 2.67, 10.7 m s (during 6.0-mhz operation) execution clock is selected (during 4.19-mhz operation) ? 0.95, 1.91, 3.81, 15.3 m s (during 4.19-mhz operation) time when subsystem 122 m s (32.768-khz operation) clock is selected i/o port cmos input 12 (on-chip pull-up resistor specified by software: 7) cmos input/output 12 (on-chip pull-up resistor specified by software) n-ch open-drain 8 (on-chip pull-up resistor 8 (on-chip pull-up resistor 8 (no mask option) input/output specified by mask option) specified by mask option) withstand voltage is 13 v withstand voltage is 10 v withstand voltage is 13 v total 32 timer 3 channels 4 channels ? 8-bit timer/event counter ? 8-bit timer/event counter 0 (watch timer output added) ? 8-bit basic interval timer ? 8-bit timer/event counter 1 (can be used as a 16-bit timer/ ? watch timer event counter) ? 8-bit basic interval timer/watchdog timer ? watch timer a/d converter ? 8-bit resolution 8 channels ? 8-bit resolution 8 channels (successive approximation) (successive approximation) ? can operate at the voltage ? can operate at the voltage from v dd = 1.8 v from v dd = 2.7 v
m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 74 parameter m pd75068 m pd750068 m pd75p0076 clock output (pcl) f , 524, 262, 65.5 khz ? f , 1.05 mhz, 262 khz, 65.5 khz (main system clock: (main system clock: during 4.19-mhz operation) during 4.19-mhz operation) ? f , 1.5 mhz, 375 khz, 93.8 khz (main system clock: during 6.0-mhz operation) buzzer output (buz) 2, 4, 32 khz ? 2, 4, 32 khz (main system clock: (main system clock: during 4.19-mhz operation or during 4.19-mhz operation subsystem clock: during 32.768-khz operation) or subsystem clock: during ? 2.93, 5.86, 46.9 khz 32.768-khz operation) (main system clock: during 6.0-mhz operation) serial interface 3 modes are available 2 modes are available ? 3-wire serial i/o mode ? 3-wire serial i/o mode msb/lsb can be selected msb/lsb can be selected for transfer first bit for transfer first bit ? 2-wire serial i/o mode ? 2-wire serial i/o mode ? sbi mode vectored interrupt external: 3, internal: 3 external: 3, internal: 4 test input external: 1, internal: 1 supply voltage v dd = 2.7 to 6.0 v v dd = 1.8 to 5.5 v operating ambient temperature t a = C40 to +85 c package ? 42-pin plastic shrink dip ? 42-pin plastic shrink dip (600 mil, 1.778-mm pitch) (600 mil) ? 42-pin plastic shrink sop (375 mil, 0.8-mm pitch) ? 44-pin plastic qfp (10 10 mm)
75 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) appendix b. development tools the following development tools are provided for system development using the m pd750068. in the 75xl series, the relocatable assembler which is common to the series is used in combination with the device file of each product. language processor ra75x relocatable assembler host machine part number os supply media (product name) pc-9800 series ms-dos tm 3.5-inch 2hd m s5a13ra75x ver. 3.30 to 5-inch 2hd m s5a10ra75x ver. 6.2 note ibm pc/at tm and refer to 3.5-inch 2hc m s7b13ra75x compatible machines os for ibm pc 5-inch 2hc m s7b10ra75x device file host machine part number os supply media (product name) pc-9800 series ms-dos 3.5-inch 2hd m s5a13df750068 ver. 3.30 to 5-inch 2hd m s5a10df750068 ver.6.2 note ibm pc/at and refer to 3.5-inch 2hc m s7b13df750068 compatible machines os for ibm pc 5-inch 2hc m s7b10df750068 note ver. 5.00 or later has the task swap function, but it cannot be used for this software. remark operation of the assembler and device file is guaranteed only on the above host machines and oss.
m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 76 prom write tools hardware pg-1500 pg-1500 is a prom programmer which enables you to program single-chip microcontrollers including prom by stand-alone or host machine operation by connecting an attached board and optional programmer adapter to pg-1500. it also enables you to program typical prom devices of 256k bits to 4m bits. pa-75p0076cu prom programmer adapter for the m pd75p0076cu and 75p0076gt. connect the programmer adapter to pg-1500 for use. software pg-1500 controller pg-1500 and a host machine are connected by serial and parallel interfaces and pg-1500 is controlled on the host machine. host machine part number os supply media (product name) pc-9800 series ms-dos 3.5-inch 2hd m s5a13pg1500 ver. 3.30 to 5-inch 2hd m s5a10pg1500 ver. 6.2 note ibm pc/at and refer to 3.5-inch 2hd m s7b13pg1500 compatible machines os for ibm pc 5-inch 2hc m s7b10pg1500 note ver. 5.00 or later has the task swap function, but it cannot be used for this software. remark operation of the pg-1500 controller is guaranteed only on the above host machines and oss.
77 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) debugging tool the in-circuit emulators (ie-75000-r and ie-75001-r) are available as the program debugging tool for the m pd750068. the system configurations are described as follows. hardware ie-75000-r note 1 in-circuit emulator for debugging the hardware and software when developing the application systems that use the 75x series and 75xl series. when developing a m pd750068 subseries, the emulation board ie-75300-r-em and emulation probe that are sold separately must be used with the ie-75000-r. by connecting with the host machine and the prom programmer, efficient debugging can be made. it contains the emulation board ie-75000-r-em which is connected. ie-75001-r in-circuit emulator for debugging the hardware and software when developing the application systems that use the 75x series and 75xl series. when developing a m pd750068 subseries, the emulation board ie-75300-r-em and emulation probe that are sold separately must be used with the ie-75001-r. it can debug the system efficiently by connecting the host machine and prom programmer. ie-75300-r-em emulation board for evaluating the application systems that use a m pd750068 subseries. it must be used with the ie-75000-r or ie-75001-r. ep-750068cu-r emulation probe for the m pd750068cu. it must be connected to ie-75000-r (or ie-75001-r) and ie-75300-r-em. ep-750068gt-r emulation probe for the m pd750068gt. it must be connected to the ie-75000-r (or ie-75001-r) and ie-75300-r-em. it is supplied with the flexible board ev-9500gt-42 which facilitates connection to ev-9500gt-42 a target system. software ie control program connects the ie-75000-r or ie-75001-r to a host machine via rs-232-c and centronix i/f and controls the ie-75000-r or ie-75001-r on a host machine. host machine part number os supply media (product name) pc-9800 series ms-dos 3.5-inch 2hd m s5a13ie75x ver. 3.30 to 5-inch 2hd m s5a10ie75x ver. 6.2 note 2 ibm pc/at and refer to 3.5-inch 2hc m s7b13ie75x compatible machines os for ibm pc 5-inch 2hc m s7b10ie75x notes 1. maintenance product 2. ver. 5.00 or later has the task swap function, but it cannot be used for this software. remarks 1. operation of the ie control program is guaranteed only on the above host machines and oss. 2. the m pd750064, 750066, 750068, and 75p0076 are commonly referred to as the m pd750068 subseries.
m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 78 os for ibm pc the following ibm pc oss are supported. os version pc dos tm ver. 5.02 to ver. 6.3 j6.1/v note to j6.3/v note ms-dos ver. 5.0 to ver. 6.22 5.0/v note to 6.2/v note ibm dos tm j5.02/v note note only english version is supported. caution ver. 5.0 or later has the task swap function, but it cannot be used for this software.
79 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) appendix c. related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to device document name document no. japanese english m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) data sheet u10165j u10165e (this document) m pd75p0076 data sheet u10232j u10232e note m pd750068 users manual u10670j u10670e m pd750068 instruction table iem-5606 C 75xl series selection guide u10453j u10453e note preliminary product information documents related to development tool document name document no. japanese english hardware ie-75000-r/ie-75001-r users manual eeu-846 eeu-1416 ie-75300-r-em users manual u11354j u11354e ep-750068cu/gt-r users manual u10950j u10950e pg-1500 users manual eeu-651 eeu-1335 software ra75x assembler package users manual operation eeu-731 eeu-1346 language eeu-730 eeu-1363 pg-1500 controller users manual pc-9800 series eeu-704 eeu-1291 (ms-dos) base ibm pc series eeu-5008 u10540e (pc dos) base other related documents document name document no. japanese english ic package manual c10943x semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor devices c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e electrostatic discharge (esd) test mem-539 C guide to quality assurance for semiconductor devices mei-603 mei-1202 microcontroller-related product guide Cthird party productsC u11416j C caution the contents of the documents listed above are subject to change without prior notice to users. make sure to use the latest edition when starting design.
m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 80 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
81 m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8
m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) 82 ms-dos is a trademark of microsoft corporation. ibm dos, pc/at, and pc dos are trademarks of international business machines corporation. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: standard, special, and specific. the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is standard unless otherwise specified in necs data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5

▲Up To Search▲

Price & Availability of PD750066A

	To Download PD750066A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .